Chapter 3 · Living chapter
Where decoupling capacitance turns into an impedance peak, and how to push it out of band. Three transient cases, measured against a solid-plane baseline, with every number reproducible from the downloadable netlists.
Only the 12-segment RL ring and eleven 100 nF decoupling caps carry the 1 A step. At 460 ns into the step, the rail sits −439 mV below nominal, easing to −410 mV by the end of the step window. That second number is the capacitor bank discharging, and it passes its own sanity check: 1 A × 460 ns ÷ 1.1 µF = 418 mV. The model and the hand-math agree to five percent. A 439 mV sag on a 1.0 V rail is also the model telling us, honestly, that a discrete bank alone is not enough.
500 pF of plane capacitance at the load node deepens the worst excursion to about −1.12 V and the rail rings at roughly 74 MHz — the plane cap and distribution inductance form an undamped tank. An undamped improvement is a resonator.
A 22 µF bulk cap with 30 mΩ ESR gives the tank somewhere to dissipate energy: the worst excursion shrinks to about −0.17 V, the mid-step sag collapses from −439 mV to −50 mV, and the residual ring decays. Damping is the fix, not more capacitance.
| Case | Worst excursion | Rail at 460 ns | End of window (900 ns) |
|---|---|---|---|
| A | −580 mV | −439 mV | −410 mV |
| B | −1120 mV | −417 mV | −355 mV |
| C | −170 mV | −50 mV | −16 mV |
Hand-math: 1 A × 460 ns ÷ 1.1 µF = 418 mV; simulated 439 mV (five percent).
Erratum — 2026-10-02
The original draft's "rail at 460 ns" figures (−410 / −355 / −16 mV) were end-of-window (900 ns) values, mislabeled by an extraction indexing error. A fresh reproducibility re-run reproduced the original simulations bit-for-bit and exposed the mislabel. The column now carries the true 460 ns values. The chapter's conclusions are unchanged. The corrected results are versioned as pdn_model_v2; the original file remains in the download bundle for the record.
Try it yourself
Only the 12-segment RL ring and eleven 100 nF decoupling caps. A 1 A load step spikes the rail to about -0.58 V, then the bank discharges into a slow sag: -439 mV at 460 ns. Hand-math (1 A x 460 ns / 1.1 uF = 418 mV) agrees to five percent.
Scenario summary
Claim: A discrete decoupling bank alone cannot hold a 1 A step.
Evidence: −580 mV spike, −439 mV sag at 460 ns (verified).
Explore: load current, rise time.
Fixed: topology, cap bank, ESL.
Bit-exact reproduction of the 2026-09-29 runs. v_min=-0.580085 V; v(460ns)=-0.438938 V; v(900ns)=-0.409943 V. Simulation-verified; physical board measurement pending.
Pre-computed from the actual ngspice netlists that produced this chapter's figures. Re-run and bit-verified 2026-10-02.
Live parameter editing arrives in a later phase — until then, download the netlists and re-run everything offline in ngspice (free).
Live experiment
Edit a safe subset of PDN parameters and re-run the simulation in your browser. Your trace appears in grey over the blue ESTABLISHED baseline.
Droop scales with load current.
Inductive spike ~ L*di/dt: faster edges bite harder.
Model integrity: this panel uses a lumped RLC model. It is valid for anti-resonance behavior up to a few hundred MHz. Results outside that range are exploratory only.
Simulation settings
Model: pdn_model_v2. Solver regime: transient 0–900 ns (.TRAN 1n 900n), ngspice defaults (trapezoidal, reltol 1e-3, abstol 1e-12, vntol 1e-6) — same as the verified runs. Timeout: 10 s.
This is a lumped RLC PDN model, trustworthy to a few hundred MHz. Layout and ESL effects beyond that are not claimed.