The target device was an Artix-7 XC7A35T in the CPG236 package: 236 balls, 10 × 10 millimeters, 0.5 mm pitch — a dense ball-grid array where every supply connection is hidden beneath the chip after assembly. You cannot see a routing mistake under a BGA. You can only prevent one before the board exists.
The map looked professional. Thirty-four rows. Ball designations, pin names, voltage rails, bank assignments, decoupling notes. Clean formatting, plausible engineering vocabulary. It named the rails correctly. It even assigned VCCINT, the core supply, to two ball locations with tidy confidence.
Both of those locations were ground pins.
Had that map been turned into copper, the 1.0-volt core rail would have been soldered directly to the ground plane through two solid metal connections. Power-on would have been a dead short across the FPGA's most tightly regulated supply. The full audit found that 32 of the map's 34 rows were wrong.
A power map is a claim, not a fact. Verify it against the vendor's package file before a single via is placed.
This was not a careless engineer's map. It was a machine-generated map: fluent, formatted, confident, and false. And it is the single most instructive artifact in this entire book.